In this paper, we show the generalized method of the time-domain circuit simulation based on LIM. Our method is applicable to any structure of circuits by combination with the SPICE-like method. In order to show the validity and efficiency of our method, an example circuit is simulated and the proposed method is compared with the conventional ones.

The effect of the power/ground plane on the through-hole signal via is analyzed in a viewpoint of a band-stop filter. When the through-hole signal via passes through the power/ground plane, the return current path discontinuity of the through-hole signal via occurs due to the high impedance of the power/ground plane. Since the high impedance is produced by the power/ground plane resonance, it acts as a band-stop filter, which is connected to the signal trace in series. Therefore, the power/ground plane filters off its resonance frequency component by absorbing and reflecting from the signal on the through-hole signal via, and consequently the signal distortion, the power/ground plane noise voltage, and the consequent radiated emission occur. With S-parameter and TDR-TDT measurements, the band-stop effect of the power/ground plane on the through-hole signal via is confirmed. And then, this analysis is applied to the clock transmission through the through-hole signal via to obtain the clearer confirmation. The measurements of the distorted clock waveforms, the induced power/ground plane noise voltages, and the radiated emissions depending on the power/ground plane impedance around the through-hole signal via are shown.

In the move toward higher clock rates and advanced process technologies, designers of the latest electronic products are finding increasing silicon failure with respect to noise. On the other hand, the minimum dimension of patterns on LSIs is much smaller than the wavelength of exposure, making it difficult for LSI manufacturers to obtain high yield. In this paper, we present a solution to reduce power-supply noise in LSI microchips. The proposed design methodology also considers design for manufacturability (DFM) at the same time as power integrity. The method was successfully applied to the design of a system-on-chip (SOC), achieving a 13.1-13.2% noise reduction in power-supply voltage and uniformity of pattern density for chemical mechanical polishing (CMP).